Staff Silicon Design Engineer – Physical Design

Your tasks

Join our Singapore silicon design team across PnR, STA and physical design integration, supporting the full lifecycle from design handoff to timing convergence, physical verification and signoff. Depending on experience, you may own blocks, subsystems, STA or higher-level integration. AI-assisted and agentic workflows are central to how we work, and you'll use them with automation and modern EDA tools to accelerate delivery and improve quality.

• Own or contribute to RTL/netlist-to-GDS implementation: floor planning, power planning, placement, CTS, routing, optimization, ECOs and closure.
• Drive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development.
• Support hierarchical physical design and integration at block, subsystem and top level.
• Resolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification.
• Support signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR.
• Build reusable automation in Tcl, Python, Perl or shell.
• Use AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it.
• Collaborate with RTL, circuit, integration, CAD and global engineering teams.

Requirements

THE PERSON You enjoy solving complex physical design problems and understanding how logic, timing, physical implementation, power, verification and integration interact. You combine strong engineering fundamentals with an automation-first,AI-centric mindset, using scripting and AI-assisted techniques to analyze design data, improve workflows and build reusable solutions. You are data-driven, own problems from analysis through closure, and apply sound engineering judgment to independently validate everything AI produces.

PREFERRED EXPERIENCE

• Hands-on experience in one or more of: PnR, STA and timing closure, SDC development, physical design integration, physical verification and signoff, low-power design, EM/IR.
• Synopsys and/or Cadence tools, such as Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC or Calibre.
• Experience debugging complex design or flow problems.
• Advanced nodes and hierarchical designs are an advantage.
• Experience building reusable flows or methodologies is highly desirable.

Other

LOCATION Singapore