Senior Verification Engineer

End-to-End Ownership: Own the verification lifecycle from specification review and test planning through environment development, regression execution, debug, and coverage closure. Environment Architecture: Build, maintain, and scale advanced verification environments using SystemVerilog and UVM. Advanced Verification: Implement Assertion-Based Verification (SVA) to catch deep architectural bugs and simplify debug cycles. Test & Coverage Execution: Write constrained-random and directed test suites. Define, track, and close functional and code coverage metrics. Automation & Scripting: Leverage Python in a Linux environment to build regression suites, automate tool flows, and parse simulation logs efficiently. Collaboration: Work closely with RTL designers and architects to review specifications, debug RTL and testbench failures, identify root causes, resolve functional issues, and improve overall design quality. הזדמנות להצטרף לסטארט אפ קטן בצמיחה , אנשים מקסימים, תפקיד עם המון השפעה

Experience: 4 to 8 years of proven experience in ASIC/SoC design verification. Methodologies: Deep, hands-on expertise in UVM, SystemVerilog Assertions (SVA) and Object-Oriented Programming (OOP) concepts. Scripting: Strong Python scripting skills for automation and data parsing. AI: Demonstrated interest in leveraging modern AI-assisted engineering tools to improve verification productivity, automation, and debugging efficiency. Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. SoC Verification: Experience moving beyond block-level to full SoC integration and subsystem verification. Embedded CPUs: Familiarity with verifying environments containing Embedded CPUs (e.g., RISC-V, ARM) and understanding processor-peripheral interactions over AXI/AHB/APB.