Research Engineer
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Machine translation — original language: Russian.Show original
Working with VHDL/Verilog hardware description languages. Working in Xilinx Vivado, ISE, Modelsim or Active HDL, MATLAB development environments. Analysis of source code for large FPGA projects. Problem searching and troubleshooting. Working with documentation in English.
Requirements
Knowledge of VHDL/Verilog hardware description languages. Knowledge of development environments: Xilinx Vivado, ISE Modelsim or Active HDL, MATLAB. Knowledge of the basics of digital signal processing (filtering, modulation, FFT, etc.). Readiness to study wireless communication standards. Experience working with external interfaces. Confident use of Linux. English language
General education; Experience: 1 year
Conditions
Optimal