Engineer/Snr. Engineer/Staff Engineer (Design Verification)

Important Note:

This advertisement is not for immediate hiring but is intended to identify suitable candidates for future openings in this position.

Job Description

• Develop and review test plans.
• Develop verification environment/testbench in Module/IP/SOC level.
• Develop verification IP and reference model.
• Implement test with randomization-based coverage driven verification methodology.
• Implement functional and functional/code coverage closure.
• Hands-on code/debug with UVM, System Verilog, Verilog and SystemC.
• Low Power verification.
• Verification automation flow.

Job Requirements

• Bachelor /Master Degree in Electrical & Electronics Engineering/Computer/IC design/equivalent.
• With IC/ASIC design verification experience on SOC, Ethernet, PCIe, DDR, USB, ARM CPU.
• Strong experience and debugging ability on System Verilog/UVM.
• Skilled in Synopsys/Cadence/Mentor Simulator and debugging flow.
• Experience on Low Power and formal verification is a plus.
• Strong in UNIX scripting with Python, Perl, makefile Cshell.
• Fast learner and a good team player.
• Candidates with more years of experience will be considered for a more senior role.

PERSOL Singapore Pte Ltd • UEN No. 200007268E • EA License No. 01C4394 •EA Registration No. R23117785 (Lok Ding Hann)

By sending us your personal data and curriculum vitae (CV), you are deemed to consent to PERSOL Singapore Pte Ltd and its affiliates to collect, use and disclose your personal data for the purposes set out in the Privacy Policy available at https://www.persolsingapore.com/policies. You acknowledge that you have read, understood, and agree with the Privacy Policy.