Senior Digital Design Engineer

Smart Silicon is looking for a Senior Digital Design Engineer with experience in RTL design to take over digital design from low-power blocks to multiple clock domains. You will take blocks from the specification phase through to RTL, synthesis, and support for sign-off, and you will act as a technical point of reference for the engineers around you.

Responsibilities:

• You write block specifications based on system architecture and requirements
• You contribute to microarchitecture definition and architecture improvement; you take an active role in design reviews
• You develop low-power RTL in SystemVerilog/VHDL and integrate blocks at the system level, emphasizing low power design techniques and area reduction
• You optimize designs for power, area, timing, and maintainability
• You work closely with verification: you define corner cases and test scenarios, identify bugs, and support coverage closure
• You synthesize blocks, including SDC writing, and collaborate with the backend team for timing closure
• You run and identify errors in Lint, CDC, and Formality checks until sign-off
• You mentor and review the work of junior engineers

Workplace Policy The successful candidate will work on-site or hybrid at one of the Smart Silicon offices (Marousi)

Required Qualifications:

• Bachelor's/Master's/PhD in Electrical Engineering or Computer Engineering (or equivalent)
• 5–7+ years of digital ASIC RTL design in SystemVerilog and/or VHDL
• Proven experience in low-power design: clock gating, operand isolation, power gating, retention/isolation strategies, UPF/power intent
• Experience in multi-clock-domain design: CDC schemes, synchronizers, reset strategy
• Experience in tape-out with knowledge of the flow from RTL to GDS
• Hands-on experience in defining constraints for Synthesis and the ability to understand timing & power reports
• Practical sign-off checks: Lint, CDC, and LEC
• Experience in writing specifications and presenting in design reviews
• Scripting (Python, Tcl, Bash/Perl); version control (Git, Perforce)
• Desirable: functional safety (e.g., ISO 26262), mixed-signal controller design, DFT knowledge

Skills

• Clear written and spoken English, especially in specifications and reviews
• Ownership: you handle your block's issues until resolution
• Willingness to mentor and support junior colleagues

Benefits: