Memory Layout Technology Leader
About the company
Renesas is expanding its investment in next-generation hybrid non-volatile memory technology and IP development to further strengthen the competitiveness of its MCUs for automotive, industrial, and IoT applications. Since hybrid non-volatile memory IP (based on Flash or Emerging memory such as MRAM, ReRAM, etc.) directly impacts MCU competitiveness, demands for higher performance, larger capacity, and higher reliability are increasing.
With the Purpose "To Make Our Lives Easier," Renesas is a global company providing embedded semiconductor solutions. Alongside more than 21,000 engineers and problem-solving professionals active in over 30 countries, we are involved in developing world-leading technologies in the automotive, industrial, infrastructure, and IoT sectors, contributing to the realization of a safer, healthier, more environmentally friendly, and smarter future.
At Renesas, "TAGIE (Transparent, Agile, Global, Innovative, Entrepreneurial)" is at the core of our corporate culture. TAGIE represents the shared values that support how we work, how we grow, and our efforts toward achieving our Purpose. This collaborative spirit and challenging mindset enable us to transform industries through semiconductor technology and contribute to the lives of people around the world.
Your tasks
・Technical Field of Responsibility Layout design of non-volatile memory IP (Flash, MRAM, ReRAM, etc.) ・Target Products MCUs for automotive / industrial / IoT ・Project Content Layout design of non-volatile memory IP based on memory cells from in-house Fab / Foundry Contributing to PPA (Performance/Power/Area) optimization of MCU products A global development environment collaborating with domestic and international memory development teams ・Responsibilities Technical leader of the memory layout design team Formulating layout strategies from IP requirements / circuit specifications Leading layout design / verification practical work
In this position, you will be responsible for the layout design of hybrid non-volatile memory IP to be integrated into future MCUs. Because you will be involved in developing core technologies that support a world-class MCU business with shipments ranging from tens of millions to hundreds of millions of units, this is a position where you can feel a significant business impact. Furthermore, Renesas' hybrid non-volatile memory IP development department actively and continuously submits papers and presents at the world's most prestigious semiconductor conferences, such as ISSCC, Symposium on VLSI Circuits, and IEDM. This is an environment where you can further refine your expertise alongside development members with high technical skills while experiencing and acquiring a broader range of memory technology skills.
Requirements
【MUST】 ・Experience in manual layout design of non-volatile memory (目安: 10+ years) ・Experience in consensus building with circuit designers and leading layout design reviews (目安: 5+ years) ・Experience collaborating with overseas partners using English
【WANT】 ・Experience in P&R design ・Experience in analog circuit design ・Experience in layout design utilizing AI
What we offer
In addition to a competitive compensation system, we offer comprehensive benefits. Details regarding benefits will be provided during the selection process.
How to apply
Why not join us in the challenge of creating the future? We look forward to receiving your application.