Last Mile Semiconductor GmbH: Senior Layout Engineer (m/f/x) (Engineer - Electrical Engineering)

Last Mile Semiconductor GmbH, a Dresden-based deep-tech startup, is developing the next generation of energy-efficient wireless connectivity solutions based on the new DECT NR+ standard. As a pioneer in the field of ultra-low power RFICs and SoCs, we are shaping the future of IoT, Industry 4.0, and Massive Machine-Type Communication (mMTC). Our chips are based on modern CMOS and FD-SOI technologies and are used worldwide for scalable, robust, and cost-effective applications. To strengthen our team, we are looking for an experienced personality in the field of IC Layout who will contribute significantly to the success of our tape-outs.

Your Role As a Senior Layout Engineer, you are responsible for the physical design of highly integrated RF and mixed-signal ICs – from the initial floorplan idea to a successful tape-out. You will work closely with our RFIC, analog, digital, and system teams and contribute your know-how to complex layout challenges.

Your Tasks

• Independent design of IC layouts for RF, analog, and mixed-signal blocks
• Implementation of high-performance layout techniques (matching, symmetry, shielding, parasitics control)
• Creation of floorplans and block-level layouts for complex SoCs
• Execution of layout verification (DRC, LVS, ERC)
• Setting up and operating advanced layout tools (parasitic extraction, electromigration and IR drop)
• Close cooperation with design engineers to optimize performance and yield
• Analysis and debugging of layout-related problems during the verification and bring-up phase
• Support of tape-out activities
• Collaboration in the further development of layout guidelines and methodologies
• Documentation and know-how transfer within the team

Technologies & Standards

• RFIC Design & Layout
• Mixed-Signal IC Design
• CMOS / FD-SOI technologies (22FDX)
• DECT NR+ wireless standard
• EDA Tools: Cadence Virtuoso, Calibre (DRC/LVS/PEX), Assura
• Parasitic Extraction & EM Awareness
• Analog Layout Techniques: Matching, Common-Centroid, Guard Rings
• Low-Power Design & Ultra-Low-Power Architectures
• Tape-out Flow & Foundry Interfaces

Your Profile

• Completed studies in electrical engineering, microelectronics, or comparable
• Several years of experience in IC Layout (analog / RF / mixed-signal) – ideally in an industrial environment
• Deep understanding of: - Layout parasitics and their influence on performance
• Matching strategies and layout optimization
• Substrate noise, crosstalk, EM effects
• Confident handling of Cadence layout tools and verification flows
• Experience with advanced technology nodes (CMOS / FD-SOI) is an advantage
• Structured, precise, and quality-oriented way of working
• Ability to work in a team and strong communication skills in interdisciplinary teams
• Good English skills (German is an advantage)

We offer:

Freedom of Design & Responsibility

• Plenty of creative freedom and real ownership instead of micromanagement
• Short decision-making paths and direct influence on strategic decisions
• Visible contribution to the success of our product and company
• The opportunity to take on a key role in a growing deep-tech company
• Collaboration on a technology that can change the future of wireless communication

Benefits

• Employer subsidy for the Deutschlandticket or DVB-Jobticket in the amount of €55.10 monthly
• Alternatively, employer subsidy for JobRad in the amount of €54.90 monthly
• Unlimited free gym usage directly in the building
• Pension scheme and occupational disability insurance with subsidies between €100 and €200 monthly

Flexibility & Working Environment

• Flexible working hours with core working hours from 10:00 to 15:00
• Hybrid working with high flexibility
• Modern hardware and professional work equipment
• Bright, modern office spaces in a central location in Dresden
• Ergonomically equipped workstations

Team & Culture

• An international team with flat hierarchies and short communication paths
• Direct exchange with management and technical decision-makers
• Colleagues who support each other and share knowledge
• Shared lunch breaks and regular team events
• A corporate culture in which initiative and new ideas are explicitly welcome

Keywords: DECT, NR+, 5G, IOT, Microcontroller, microcontroller, Hardware, smart, Startup, Elektrotechnik, VHDL, Verilog, ASIC, ASIC Engineer, Dresden, SoC, Semiconductor, Halbleiter, Chip, DECT NR+, FPGA, Smart Edge Connectivity, LM10XX, microelectronics, chip design, connectivity, Layout, Wireless, IC, Mikroelektronik, Empfehlungsbund Source/Application via: https://www.empfehlungsbund.de/jobs/297580/senior-layout-engineer-m-strich-w-strich-x (https://www.empfehlungsbund.de/jobs/297580/senior-layout-engineer-m-strich-w-strich-x#apply_form) Short info about the company

We are a semiconductor startup based in Dresden, Germany - the heart of Silicon Saxony - and are developing a new, non-mobile 5G cellular chipset that enables secure, massive IoT use cases.

Driven by the vision of a future where technology is seamlessly integrated into our daily lives, including homes, industries, public spaces, and healthcare, we strive to optimize resource and energy consumption while building global digital sovereignty. To realize this vision, we are actively developing a cost-effective and extremely low-power 5G cellular chipset based on the revolutionary NR+ standard for non-mobile private 5G.

Home office: Extent: By arrangement