Senior / Staff Engineer - Digital Design

Your role Key responsibilities in your new role

• Perform RTL-to-gate synthesis using EDA tools such as Synopsys Design Compiler/Fusion Compiler or Cadence Genus to generate optimized gate-level netlists .
• Run Static Timing Analysis (STA) including setup/hold checks across pre- and post-layout stages using tools such as Synopsys PrimeTime or Cadence Tempus .
• Collaborate with design, verification, and PD teams to ensure timing closure and design optimization .
• Assist in the development and maintenance of synthesis and STA scripts and methodologies .
• Analyze and resolve timing issues , working closely with cross-functional teams.
• Run timing constraint checks and logic equivalency checks (LEC).
• Participate in design reviews and provide feedback on timing and synthesis aspects.
• Document and report synthesis and STA results , highlighting key findings and recommendations .

Your profile Qualifications and skills to help you succeed

• Bachelor’s/Master’s degree in Electrical Engineering , Computer Engineering , or a related field .
• At least 3–5+ years of hardware engineering (or related) experience.
• Hands-on experience with logic synthesis , LEC , STA , timing constraints , and timing convergence .
• Expertise in timing closure via ECOs , including crosstalk and noise analysis .
• Background in physical design and optimization (e.g., placement , routing , cell sizing ) to improve timing and power .
• Ability to run basic PD steps such as floorplanning and placement using ICC2 or Innovus (plus).
• Proficiency in scripting ( Python , Tcl , Perl ) for automation .
• Excellent verbal and written communication skills.