Senior Engineer - Integration Engineering
Nice-to-have:Python
Your tasks
Key responsibilities in your new role
- Work in the R&D Mixed-Signal IC design organization
- Become a key enabler for Mixed-Signal IP Integration into the Sub-System or System on Chip (SoC), with regards to requested design views from the customer
- Act closely with the subsystem/SoC teams on the right power/timing/netlisting strategy for IP integration
- Define the proper IP integration method for analog/digital or mixed-signal blocks
- Debug and solve issues with regards to mixed-signal IP integration
- Drive improvements of the state-of-the-art mixed-signal IP delivery methodologies
- Guide and support IP designers for usage of the state-of-the-art integration methods
Requirements
Qualifications and skills to help you succeed
- A university bachelor or master degree in Electrical/Electronics Engineering, Computer Science, or equivalent
- At least 3-5 years of experience in digital, analog, or mixed-signal design
- Experience with Cadence Virtuoso or Cadence/Synopsys RTL2GDS tools
- Experience with CAD methodology for digital and/or analog design and integration
- Knowledge of UPF and Digital IP power strategy
- Programming or scripting skills such as Perl, TCL, Python, or Skill is a plus
- Knowledge of HDL languages (System Verilog, VHDL) and experience with Unix/Linux
- Strong debugging skills
- Solid networking and customer-oriented soft skills
- Good English verbal and written skills are mandatory