Senior Test Engineering Manager

Job Summary

The Senior Test Engineering Manager will provide strategic leadership, technical vision, and personnel management for the test engineering team. This position is responsible for end-to-end manufacturing test architecture, including In-Circuit Testing (ICT), Boundary Scan (JTAG), Functional Testing (FCT), and system-level burn-in racks under environmental conditions.

The ideal candidate will serve as a bridge between hardware test design and mass production execution, ensuring maximum test coverage, rapid root cause diagnostic capabilities, and robust data automation to achieve high first-pass yield targets across multiple production lines.

Key Responsibilities

1. Strategic Leadership and Test Infrastructure Management

• Engineering Team Management: Direct, mentor, and develop a team of test engineers and validation technicians working across multiple shifts. Establish clear responsibilities, technical training plans, and competency matrices.
• Test Strategy and Investment Planning: Define the technical roadmap for the factory's test infrastructure. Draft comprehensive Capital Expenditure (CapEx) specifications for new Automated Test Equipment (ATE), high-speed traffic generators, and custom environmental test racks.
• "Copy Exact" Synchronization: Enforce absolute technical discipline across all testing operations by establishing and auditing "Copy Exact" protocols for test software configurations, diagnostic scripts, and fixture calibration limits.

1. Technical Execution and High-Speed Network Validation

• Multi-stage Test Optimization: Oversee the continuous development and tuning of ICT (Keysight/Teradyne) test limits, JTAG, and functional data routing gates to prevent false failures while maintaining comprehensive fault coverage.
• High-Speed Traffic Integration: Oversee automation scripts and test sequences that verify signal integrity, optical transceivers, and lossless traffic routing using enterprise network test architectures (e.g., Ixia, Spirent, or native ASIC closed-loop testing).
• Diagnostic and Failure Analysis Leadership: Act as the final escalation point for complex technical failures. Guide the engineering team through exhaustive debugging of multi-layer Printed Circuit Board Assembly (PCBA) failures, firmware injection failures, and drops during high-temperature burn-in.

1. Data Automation and Continuous Performance Improvement

• First Pass Yield (FPY) Optimization: Continuously monitor real-time performance dashboards. Collaborate with process and operations teams to immediately contain yield deviations and drive permanent engineering solutions.
• Data System Integration: Oversee the connection between automated test scripts and the factory Manufacturing Execution System (MES), ensuring impeccable traceability of MAC addresses, firmware versions, and localized parametric data.
• Gauge Repeatability and Reproducibility (R&R) Stability: Enforce strict maintenance and periodic validation of gauge repeatability and reproducibility across all test devices to ensure system stability and prevent production line disruptions.

Requirements and Required Competencies

• Education: Bachelor's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, or a closely related technical field. A Master's degree (MS) is highly valued.
• Experience: 8 to 10+ years of experience in hardware test engineering within advanced electronics manufacturing (e.g., network switches, high-performance enterprise servers, telecommunications infrastructure), with at least 3 years in a direct management or supervisory role.
• Technical Domain Experience:
• Expert knowledge of structural test platforms (ICT/Flying Probe) and system-level electronic system functional validation.
• Deep knowledge of Linux-based Network Operating Systems (NOS), network topologies, and high-speed data transmission standards.
• Proficiency in hardware control automation environments using Python, LabVIEW, or NI TestStand.
• Methodologies: Solid experience in Statistical Process Control (SPC), yield optimization via Pareto diagrams, and structured failure analysis (8D, Ishikawa, 5-Why).

Key Performance Indicators (KPI) for Success

• First Pass Yield (FPY) Stability: Maximize line throughput by maintaining high and stable first-pass yields through regular test fixture tuning and preventive maintenance.
• OEE and Test Equipment Uptime: Maintain critical diagnostic stations and automated test benches operating at over 96% availability.
• New Product Introduction (NPI) Transition Milestones: Timely implementation and qualification of newly developed test equipment and automation sequences prior to pilot and mass production launch dates.

Advanced Conversational English

Preferably with experience in the electronics or electronic card industry. -Requirements- Minimum Education: Higher Education - Bachelor's Degree 10 years of experience Languages: English Age: between 35 and 59 years Keywords: lider, jefe, gerente, manager, director, chief, lead, jefatura, regente, senior, sr, engeneering, ingenieria