FPGA Designer

Development and debugging of FPGA projects. Documentation of developed projects.

Requirements

Higher (technical) education, preferably in the field of radio engineering. At least 3 years of experience in the development and debugging of FPGA projects. Experience in project development in Vivado/ISE/Quartus (choice of one). Experience in modeling developed projects in Modelsim/Vivado/ISE simulators (choice of one). Knowledge of VHDL/Verilog/System Verilog (choice of one). Knowledge of the fundamentals of digital circuit design. English language proficiency at the level of reading technical documentation. Occasional business trips are possible. Advantages will be: Ability to perform timing optimization of developed projects. Knowledge of scripting languages TCL, Python. Knowledge of the TCP/IP network protocol stack. Experience working with Wireshark. Experience working with 10/100/1000 Gbit Ethernet, DDR2/DDR3.

Higher education — Bachelor's degree; Experience: 3 years