DSP Engineer Category 2
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Machine translation — original language: Russian.Show original
Software development for ALTERA and XILINX FPGAs. Work schedule: Mon.-Fri. from 07:45 to 16:45, lunch from 12:00 to 13:00.
Requirements
Higher technical education, at least 3 years of work experience. Working with QUARTUS EDA. Knowledge of AHDL, VHDL languages. Ability to read and analyze technical documentation. English language (reading documentation).
Higher education — Bachelor's degree; Experience: 3 years
Conditions
Permissible