Lead Design Engineer

АО "НИИЭТ"Воронежtrudvsempublished 09/02/2026

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Must-have:Git

Machine translation — original language: Russian.Show original

Development of verification plans for testable modules and devices as a whole; Implementation of verification environment components according to specified requirements; Implementation of components for functional coverage measurement according to specified requirements; Implementation of tests according to the verification plan; Documentation and support for bug fixes in RTL models of SF-blocks; Testing of RTL models of blocks, the RTL model of the device as a whole, and the synthesized electrical circuit (netlist) with delays (sdf), and fault analysis.

Requirements

Higher technical education; Work experience of 5 years or more; Knowledge and understanding of the fundamentals of digital circuit design; Knowledge of Verilog/SystemVerilog/VHDL, C languages; Experience working with simulation EDA tools; Technical English; Knowledge of UVM principles, skills in developing and assembling test environment components; Knowledge of version control systems (SVN, GIT).

Higher education — specialist degree, master's degree; Experience: 6 years