DFT Architect

Your tasks

Testing a single die is hard enough. Testing a system of chiplets means rethinking test access, coverage and diagnosis from the ground up. You'll define the DFT architecture for complex, multi die designs and make sure it works hand in hand with physical design.

• Define DFT architecture and strategy for SoC and chiplet based designs
• Own test access across dies, including JTAG, IJTAG and IEEE 1500/1838 approaches
• Set ATPG and scan compression strategy to meet coverage and test cost targets
• Work closely with physical design on DFT timing, placement and routing impact
• Drive test coverage analysis and improvement across the chip
• Lead DFT methodology, reviews and mentoring for the DFT team
• Support silicon bring up and diagnosis

Requirements

• 10+ years of DFT experience, including architecture level ownership
• Deep knowledge of ATPG, scan compression, JTAG, MBIST and LBIST
• Experience with chiplet or multi die test strategies is a strong plus
• Solid understanding of physical design and how DFT affects it
• Experience with Tessent, Synopsys or Cadence DFT tools
• Scripting in Tcl, Perl or Python
• Strong technical leadership skills

• You think about test from the first architecture meeting, not the last
• You enjoy solving problems that don't have a textbook answer yet
• You work as comfortably with PD engineers as with test engineers
• You measure your success in coverage and in silicon results
• You want to lead DFT strategy for the next generation of designs