IC Layout Engineer
Nice-to-have:Python
- Collaborate with design engineers to prepare IC layouts for tapeout on one or more of technologies: SiGe,CMOS, SOI and GaAs, GaN
- Perform Cell and Chip level schematic entry, IC layout, and verification (LVS, DRC, ERC) for RFICs
- Floorplan, chip layout, routing and verification and support/assist in tapeout
- Develop documentation and training materials
Qualifications
- Bachelor of Science Degree, or equivalent experience
- 5+ years of work experience
- Relevant experience and a willingness to learn is necessary.
- Proficiency with CAD tools such as Cadence Virtuoso, Mentor Graphics Calibre; and AWR, Keysight ADS
- Experience with: Linux and Windows computer systems.
- Linux shell scripts, Skill, AMPLE, Perl, Python is a plus.
- Candidate must be self-driven, detail-oriented and eager...