RTL / UVM Verification Engineer (M/F) - CDI

Salary: 48k€ - 50k€

We are supporting a leading international player in the development of innovative solutions for complex electronic systems (SoC - System on Chip). Its technologies are used in cutting-edge sectors such as automotive, telecommunications, artificial intelligence, connected objects, or cloud infrastructures.

As part of the strengthening of its R&D teams, we are looking for a Design Verification Engineer passionate about RTL verification and next-generation development environments.

Within a team of experts, you will work on the design and validation of tools intended for the most advanced SoC assembly flows.

Your role consists of guaranteeing the reliability, quality, and robustness of the developed solutions, while contributing to the continuous improvement of verification methods and engineering processes.

Master's degree (Bac+5) in computer science, electronics, or embedded systems.

Significant experience of 7 years in RTL verification and wishing to evolve in a demanding technological environment.

Technical skills:

• Excellent mastery of RTL verification.
• Very good knowledge of the UVM (Universal Verification Methodology) framework.

• Mastery of SystemVerilog, Verilog, and VHDL languages.
• Solid skills in Python and object-oriented programming.

• Experience with Cadence, Synopsys, or Siemens EDA simulation environments.
• Good understanding of continuous integration practices and test automation.

• Fluent professional English, written