Senior/ DFT Engineer (Silicon)
Senior
Key Responsibilities
- Develop and deliver test program and scan test patterns for IP and SOC designs.
- Improve scan test architecture, test coverage and overall product quality.
- Analyze and debug ATPG patterns, test models and gate-level netlists.
- Work with cross functional teams to resolve timing, clock, power and design issues.
- Support DFT requirements for high-speed designs while minimizing performance impact.
- Troubleshoot complex design and integration issues across IP and SOC platforms.
- Improve existing design and testing processes to enhance engineering efficiency.
Requirements
- Degree in Computer/Electronics engineering or equivalent with minimum 1 year of relevant working experience.
- Experience in Design-for-Test (DFT), particularly Scan Test and ATPG.
- Hands-on experience with Tessent or other industry-standard ATPG tools.
- Strong knowledge of scan testing, pattern generation and fault coverage.
- Experience debugging scan patterns, test models and gate-level netlists.
- Understanding of IEEE 1149.1, IEEE 1500 and MBIST.
- Experience supporting high-speed designs such as SERDES, PHY, Ethernet advantages.
We invite suitable candidates to apply online or email your CV to resume@aurexis-tech.com