ASIC Design Tutor

Responsibilities:

Teach students how to develop, enhance, and debug VHDL and Verilog/SystemVerilog code for chip designs.

Train students to verify design functionality on HDL simulators such as ModelSim, QuestaSim, or Xcelium, and to run synthesis with Synopsys or Cadence Genus.

Teach clock domain crossing (CDC) and reset domain crossing (RDC) verification.

Teach Design for Test (DFT), including adding memory BIST and JTAG scan chains to a design.

Guide students in developing and porting RTL to an FPGA prototyping board.

Teach place and route of the netlist before tapeout, including clock tree synthesis (CTS).

Train students to run static timing analysis (STA) and power analysis after CTS and place and route.

Cover packaging and evaluation board requirements for the physical chip.

Develop training materials, labs, and practical exercises, and adapt lessons to each student's skill level and goals.

Requirements:

Proven experience developing in VHDL and Verilog (or SystemVerilog).

Experience targeting VHDL designs to Xilinx FPGAs.

Experience using ModelSim/QuestaSim.

Experience using Cadence Virtuoso.

Working knowledge of synthesis, CDC/RDC, DFT, place and route, CTS, and STA.

Strong communication skills and the ability to explain complex technical concepts clearly.