Staff ASIC Digital Engineer (STA and Sign-Off)

Accountabilities: Own and drive complete STA sign-off activities for ASIC designs, ensuring timing closure and design readiness for tape-out.

Provide technical guidance to Physical Design and Place & Route teams on timing closure strategies and synthesis report analysis.

Collaborate with IP, RTL, and design teams to develop, review, and optimize timing constraints and sign-off methodologies.

Develop and implement advanced STA methodologies to meet the performance requirements of highly complex semiconductor designs.

Perform detailed timing analysis, identify critical timing paths, and propose effective solutions to resolve timing violations.

Create, enhance, and maintain STA scripts, automation frameworks, and tools to improve efficiency and scalability.

Work closely with cross-functional teams, including verification, DFT, and physical implementation teams, to ensure seamless design integration.

Prepare and present technical reports, timing sign-off documentation, and status updates to key stakeholders.

Drive continuous improvement initiatives by incorporating industry best practices and emerging timing analysis techniques.

Mentor engineering teams and foster a culture of collaboration, innovation, and technical excellence.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics, or a related discipline.

Minimum of 8 years of experience in Static Timing Analysis and ASIC timing sign-off activities.

Proven experience leading end-to-end STA sign-off for complex semiconductor projects.

Strong expertise with industry-standard STA tools such as Synopsys PrimeTime, Cadence Tempus, and Constraints Manager.

Deep understanding of digital design principles, synthesis, physical design flows, and semiconductor manufacturing processes.

Hands-on experience guiding engineering teams through timing closure challenges and sign-off readiness.

Strong analytical and problem-solving skills with the ability to develop strategic solutions for complex timing issues.

Excellent communication and collaboration skills, with experience working across multidisciplinary engineering teams.

Ability to manage multiple priorities and deliver results in fast-paced and technically demanding environments.

Experience with advanced semiconductor process nodes such as 5nm and 3nm is highly desirable.

Proactive mindset with a passion for innovation, continuous improvement, and technical leadership.

Benefits

Opportunity to work on cutting-edge semiconductor technologies and advanced process nodes.

Exposure to highly complex ASIC programs with significant technical ownership and impact.

Collaborative and inclusive work environment that values innovation and diverse perspectives.

Career growth opportunities through challenging projects and global engineering exposure.

Access to advanced tools, technologies, and industry-leading engineering practices.

Supportive culture focused on professional development and continuous learning.

Inclusive workplace committed to equal opportunities and accessibility for all employees.

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