Package Pathfinding Architect, MTS
Package Pathfinding Architect We are the team defining the future of packaging of complex memory systems! Our Package pathfinding and Architecture organization sits at the intersection of silicon, packaging, systems, and customer needs—turning complex scaling challenges into technologies that power next‑generation platforms, through cutting edge packaging technologies. If you enjoy working on problems with real industry impact, look no further. This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end‑to‑end memory system architectures, to guide long‑term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron. Main Responsibilities: Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance.
Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach
Drive long‑term memory technology packaging strategy and influence industry standards
Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge-AI and datacenter memory products
Serve as a technical interface to internal partners, customers, BUs, senior leaders.
AI Responsibilities: Develop AI based EDA and internal automation tool sets for enhancing design cycle efficiency.
Develop measurement automation for incoming substrate materials
Candidate Profile or Job Requirements/Qualification/Selection Criteria: Details on what is required of the successful candidate. Minimum Qualifications: Master’s degree or equivalent degree and industry experience in EE, CE, CS, or related field
At least 5 years of relevant industry experience in package design, electrical simulations and tools like Ansys, Siemens and Cadence
Extensive hands‑on experience in memory systems package design, signaling, IO design, PDN design
Deep understanding of memory timing, signaling, power, package process technology
working knowledge of EDA tools for design, analysis and simulation of electronic packaging, including but not limited to Cadence, Siemens and Ansys tools
Experience applying AI or LLMs for engineering efficiency
Preferred Qualifications: PhD in a related technical field
Recognized technical leadership across multiple products
Experience in Signal and Power integrity analysis and mechanical and reliability analysis, thermal analysis
Expertise in memory systems architecture
Must Have Technical Skills, if any Strong understanding of memory timing and analysis
Experience with Memory package and memory die level specs
Familiarity with signal and power integrity concepts and tool.
Proficiency in data analysis tools such as JMP, Python, or MATLAB.
Must Have Soft Skills, if any Strong analytical and problem-solving skills with a data-driven mindset.
Effective communication skills for cross-functional collaboration with engineering, operations, and quality teams.
Detail-oriented with a commitment to quality and continuous improvement.