FPGA Design Engineer
Long Wall Company was created in 2024 to accelerate missile defense technology for the U.S. and our allies. Building on the RS1 and GS0 launch systems, Long Wall develops containerized, mass-producible missile defense systems and offers rapid, low-cost flight testing. We believe that the future of global security and stability require defensive technology that is lower cost, higher performing, better tested, and more broadly distributed than is possible today. Join us.
What we look for Mission-Driven Problem Solvers. The aerospace frontier demands ingenuity. We want Team members who approach challenges with curiosity, embrace failure as a learning opportunity, and stay focused on delivering the best solution for the mission.
Total Ownership. We seek staff and engineers who take full responsibility for contributing to and delivering flight-ready work while recognizing that no one succeeds alone. The best engineers, corporate professionals, and technicians make their teammates better. Knowing that complementary skills create force multiplication and drive mission success.
RESPONSIBILITIES: Design, implement, and verify FPGA firmware for (Xilinx) AMD-based systems, including SoC and ACAP architectures
Debug and validate firmware through hardware-in-the-loop testing and system integration
Collaborate with hardware engineers to define FPGA I/O requirements and board-level interfaces
Collaborate with software engineers to design CPU driver interfaces for custom IP cores
Create and maintain technical documentation, including design specifications, timing reports, and test plans
Contribute to architecture decisions for FPGA/embedded systems and participate in design reviews.
BASIC QUALIFICATIONS: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of hands-on FPGA development experience with AMD/Xilinx platforms
REQUIRED SKILLS AND EXPERIENCE: Expert-level knowledge of Xilinx FPGA architectures and Zynq SoC platforms
Strong understanding of digital design principles, timing analysis, and clock domain crossing techniques
Experience with Xilinx Vivado design suite for synthesis, implementation, and debugging
Demonstrated ability to bring FPGA designs from concept through production
Extensive experience with troubleshooting designs and resolving integration issues.
Excellent communication and presentation skills.
Proficiency in HDL languages (VHDL and/or Verilog/SystemVerilog)
Proven experience with Vivado and Vitis toolchains, including IP integration, timing constraints, and build automation
Experience developing custom IP cores with register interfaces, interrupt generation, and DMA engine integration
Understanding of high-speed serial interfaces (SerDes/SERDES) and multi-gigabit transceiver architectures
Strong knowledge of streaming video/data architectures, including buffering strategies, flow control, and memory management
Implementation of high-speed communication protocols: PCIe (Gen 1/2/3/4/5), 1G/10G/25G Ethernet MAC/PHY layers (SGMII, RGMII, UXSGMII)
Design and optimization of streaming DMA architectures and high-throughput data paths
Multi-clock domain design, including proper CDC (Clock Domain Crossing) techniques and metastability mitigation
Ability to collaborate with software engineers on hardware/software interfaces, including memory-mapped register design and interrupt architecture
Strong debugging skills using Vivado ILA, VIO, and hardware test equipment (oscilloscopes, logic analyzers)
Proficiency with version control systems (Git) and CI/CD workflows for FPGA development
PREFERRED SKILLS AND EXPERIENCE: Master's degree in electrical engineering, computer engineering, or related field
Develop high-performance data paths and interfaces, including PCIe, Ethernet, and streaming DMA systems
Experience with Versal ACAP systems and Network-on-Chip (NoC) design requirements and profiling
Experience with Xilinx High-Level Synthesis (HLS) for algorithm acceleration
Experience with Versal AI Engine development and optimization
Knowledge of AXI/AXI-Stream protocols and custom IP core development
Experience with video processing pipelines, frame buffering, and line buffering architectures
Understanding of driver development concepts and register-level programming interfaces
Familiarity with embedded Linux and Xilinx PetaLinux for Zynq systems
Experience with signal processing algorithms and DSP optimization on FPGAs
Understanding of power optimization techniques for FPGA designs
Python/TCL scripting for design automation and verification
Exposure to functional verification methodologies and simulation tools (ModelSim, Vivado Simulator)
Experience with board bring-up and hardware/software co-design
Experience with hardware-in-the-loop (HIL) test methodologies and integration
ADDITIONAL REQUIREMENTS: Ability to sit or stand for extended periods of time
Ability to use a computer to complete assignments
Ability to communicate with individuals and groups in person, by phone and telepresence
Ability to pick up to 12lbs
While performing the duties of this job, the employee will typically work in an office environment
ITAR Requirement This position requires access to information protected under US export control laws, including the International Traffic in Arms Regulations and/or the Export Administration Regulations. As such, US person status (including US citizens, U.S. permanent residents, individuals granted U.S. asylum status, or individuals admitted in U.S. refugee status) is a required qualification for this position.
Equal Opportunity Employer We are an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, protected veteran status, disability, genetics, or citizenship status (when otherwise legally authorized to work and access export-controlled data) and will not be discriminated against on the basis of such characteristics or any other status protected by the laws or regulations in the locations where we operate. We encourage applicants of all ages.