Senior Embedded Systems/IoT Hardware Architect (Fixed-scope for expert: 100 hours over 4 weeks, 25 h/week (fractional))

Item

Detail

Role

Senior Embedded Systems / IoT Hardware Architect

Contract type

B2B (Jednoosobowa działalność gospodarcza — sole proprietorship)

Duration

4 weeks from commencement, with a planned extension into certification-support and design-transfer phases

Allocation

25 hours/week (~5 hours/day; candidate controls their own schedule, provided a daily ~30-minute sync window overlaps with the Client), 100 hours total

Location

Remote (Poland-based; candidate must have access to own electronics lab)

Remuneration

170–200 PLN/h (~40–47 EUR/h); up to 200 PLN/h (~47 EUR/h) for candidates with prior CB Scheme submission experience — invoiced weekly, paid within 2 working days

Weekly equivalent

4,250–5,000 PLN gross/week (~990–1,160 EUR) based on 25 h/week

Total contract value

17,000–20,000 PLN (~3,950–4,650 EUR) for the 4-week / 100-hour engagement

Follow-on

Planned DFM support retainer (~10 h/month at the same rate) plus two further hardware projects in the pipeline for a proven performer

Daily tasks

• 1. Written verification audit report with prioritized remediation plan (Phase 1)
• 2. Updated PCB design files (source + Gerbers) with corrected HV multiplier topology, production power supply, and EMC/isolation improvements
• 3. Updated firmware repository with BLE stability fixes, documented build environment
• 4. SMT-ready manufacturing package (centroid files, panelization, fiducial documentation)
• 5. Certification readiness documentation package for IEC 60601-1 / CB Scheme submission
• 6. Final handover: walkthrough session and recorded summary of outstanding risks
• Priority rule: If, by the end of Week 3, Tier 1 work (Phase 2) has consumed more than 85% of total contracted hours, Tier 2 deliverables move to an agreed extension week at the same hourly rate — decided jointly by the Parties and confirmed in writing, not deferred silently.
• Respin carve-out: Any remediation identified in Phase 1 that can only be physically validated on a newly fabricated PCB (respin) shall be delivered as design + validated simulation within this engagement; physical prototype validation shall be scoped separately and is explicitly excluded from the 4-week duration.

Requirements

Core Requirements (Candidate Profile)

Mandatory:

• Proven experience preparing electronic products for IEC 60601-1 or IEC 62368-1 laboratory testing
• Native Espressif ESP-IDF and NimBLE experience is essential; Arduino-framework-only backgrounds are not suitable for this engagement
• Expertise in PCB design/layout optimization for EMC compliance (shielding, galvanic isolation, 2xMOPP requirements, split ground planes)
• Experience formatting files for automated SMT assembly lines (centroid data, fiducials, panelization)
• Must possess an independent, fully-equipped home hardware testing laboratory (oscilloscope, logic analyser, and relevant test equipment)

Preferred:

• Prior involvement in CB Scheme or MDR regulatory submissions (qualifies for the top of the rate band: 200 PLN/h / ~47 EUR/h)
• Familiarity with high-voltage / voltage-multiplier circuit design
• Experience with BLE coexistence and EMI debugging in mixed-signal designs

Must have: nimble, • Native Espressif ESP-IDF, Arduino-framework, PCB design, layout optimization for EMC compliance, automated SMT assembly lines, electronic products for IEC 60601-1 or I

Nice to have: CB Scheme, MDR regulatory submissions, BLE coexistence, EMI debugging