Senior NVM Designer

Mythic· Palo Alto, CA· lever· birt 05.08.2026
Skilyrði:PythonBackend

What you'll do Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available NVM technologies from foundries

Involve in NVM architecture for optimum performance and area

Design and verify the new circuits to handshake with the analog computation blocks

Design, optimize and verify the NVM circuits including and not limited to high voltage generator block, x-path, y-path, test and peripheral circuits

Participate in RNM and functional model of NVM circuits for verification

Responsible for verifying the functional blocks and full chip level interfacing with NVM design

Work closely with the validation engineers to expedite the silicon evaluation process

Work closely with backend teams for the production qualification releases

What you'll bring Ph.D. or MS degree in EE or related 5-10+ years industrial experience

Hands-on experience in NVM embedded or NVM product design and verification

Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification

Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling

Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability

Good understanding & knowledge of semiconductor device physics, and advanced process technology

Experienced in multiple generations NVM tapeout activities, layout supervision, chip planning, silicon debugging

Excellent communication skills, ability to work well across multi-functional teams

Fluent in all major CAD tools: SPICE, Cadence, Verilog simulation software

Some knowledge of scripting such as Python

Must be a self-starter, detail-oriented, and team player